This disclosure relates to integrated circuit devices (“ICs”), and more particularly to testing the performance of clock and data recovery (“CDR”) circuitry on an IC.
Many different kinds of integrated circuits (“ICs”) include clock and data recovery (“CDR”) circuitry for use, for example, in receiving a high-speed serial data signal from other circuitry in a larger system that the IC is part of. The high-speed serial data signal that is applied to such CDr circuitry on an IC may combine both serial digital (e.g., binary) data information and the clock or timing information that is needed to determine when the serial data signal is representing each successive binary digit (“bit”) of the data information. Typically this clock information is embodied in the timing of transitions between the binary levels of the serial data signal. In other words, there is no separate clock signal (having a predetermined phase relationship to the serial data signal) that accompanies the serial data signal. The serial data signal itself includes both the serial data information and the timing or clock information needed to recover the data information from the serial data signal.
CDR circuitry that receives a serial data signal of the type described above typically includes circuitry for recovering the clock or timing information from the serial data signal and producing a “recovered clock signal” embodying that recovered clock information. Such CDR circuitry typically also includes circuitry for using the recovered clock signal (or possibly a phase-shifted version of the recovered clock signal) to time sampling of the serial data signal at times that are optimal or nearly optimal for recovering successive data bits from the serial data signal. The thus-recovered serial data may be embodied in a so-called “retimed data signal” or “recovered data signal” output by the CDR circuitry.
As a somewhat more specific example of the foregoing, the CDR circuitry may be designed to attempt to sample the serial data signal as close as possible to the center of each unit interval (“UI”) in the serial data signal. (The UI is the time period during which any one of the successive data bits is present in the serial data signal). In order to do this, the CDR circuitry may try to synchronize, as nearly as possible, the frequency and phase of transitions in the recovered clock signal with the frequency and phase of transitions in the serial data signal. This may be done, for example, by the CDR circuitry controllably changing the frequency and phase of the signal that it will use as the recovered clock signal. When the above-mentioned synchronization has been satisfactorily achieved, the CDR circuitry may use a sampling clock signal with a 90 degree phase shift from the recovered clock signal to sample the serial data signal concurrently with transitions in the sampling clock signal. These sampling clock signal transitions should be at or near the center of each successive UI in the serial data signal, thereby producing the desired optimal or near optimal sampling of the serial data signal for the most reliable (i.e., most nearly data-error-free) recovery of the data information. Sampling at or near the center of UIs is typically best because that is the location along each UI that is most distant (in time) from possible changes (transitions) in the level of the serial data signal (due to possible need of that signal to represent a preceding or succeeding data bit having a different binary value (1 or 0) than the current bit). This reduces (preferably to a minimum) the risk that a sample will be erroneous due to effects from a transition in the serial data signal.
In actual use of an IC in a larger system, a serial data signal applied to the IC is rarely, if ever, completely “clean,” i.e., free from noise, attenuation of at least some frequency components, timing instability, etc. Moreover, even nominally identical ICs may have some variation in the ability of their CDR circuitry to tolerate such imperfections in a received serial data signal. For example even ICs that have been manufactured to be the same may have some such CDR variations due, e.g., to variations in the manufacturing process from one semiconductor wafer to the next semiconductor wafer or the like. ICs with greater tolerance for serial data signal imperfections may be referred to as having a greater CDR performance margin and may be saleable at a higher price than otherwise similar ICs with less tolerance for such imperfections. This can contribute to a need for efficient ways to test the CDR performance margin of ICs.